Main Page
Retina Chip Documentation System — the live, present-state knowledge base for the high-channel-count implantable neural-interface ASIC.
The diagram below is the retina chip signal chain. Click any block to open its wiki page.
About this wiki
This wiki follows two hard rules:
- Two genres, never merged — the Timeline is an immutable, append-only chronological record of what was believed on a date. Wiki pages are statements of what is true now. They are never merged.
- Durable vs instance — every block splits into a durable page (what the block is, design equations, budgeting procedure — true independent of any chip) and instance pages (component values, sizing, post-PEX numbers, errata for a specific silicon). A chip page is a thin manifest linking to its instances.
The chips in scope
| Chip | Node | Role |
|---|---|---|
| RC1.9 | TSMC 28nm HPC+ | 1024-channel wired AFE redesign; taped out |
| RC2.0 | TSMC 28nm HPC+ | wireless variant (UWB); currently active |
| PMU1 | 180nm | power-management test chip — does not inherit 28nm defaults |
| RC3.0 / RC3.1 | 28nm | future, scaled toward 10k+ channels |