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__NOTOC__ | |||
'''Retina Chip Documentation System''' — the live, present-state knowledge base for the high-channel-count implantable neural-interface ASIC. | |||
The diagram below is the retina chip signal chain. '''Click any block''' to open its wiki page. | |||
<imagemap> | |||
File:Retina-chip-signal-chain.svg|980px|center|Click any block to open its wiki page | |||
desc none | |||
rect 40 270 160 340 [[Blocks|Electrode (goes to AFE)]] | |||
rect 230 270 360 340 [[Block:AFE Gm-C|AFE Gm-C integrator]] | |||
* [ | rect 420 270 550 340 [[Block:SC LPF|Switched-cap LPF]] | ||
rect 610 270 730 340 [[Block:SAR ADC|SAR ADC]] | |||
rect 790 270 930 340 [[RC2.0|Wireless / UWB (RC2.0)]] | |||
rect 420 420 550 490 [[Block:EDO Attenuator|EDO attenuator]] | |||
rect 610 420 730 490 [[Block:Stimulator|Current-steering stimulator]] | |||
rect 250 90 400 160 [[Block:Bias Bandgap|Bias / bandgap]] | |||
</imagemap> | |||
== About this wiki == | |||
This wiki follows two hard rules: | |||
* '''Two genres, never merged''' — the [[Timeline]] is an immutable, append-only chronological record of ''what was believed on a date''. Wiki pages are statements of ''what is true now''. They are never merged. | |||
* '''Durable vs instance''' — every block splits into a '''durable''' page (what the block is, design equations, budgeting procedure — true independent of any chip) and '''instance''' pages (component values, sizing, post-PEX numbers, errata for a specific silicon). A chip page is a thin manifest linking to its instances. | |||
== The chips in scope == | |||
{| class="wikitable" | |||
|- | |||
! Chip !! Node !! Role | |||
|- | |||
| [[RC1.9]] || TSMC 28nm HPC+ || 1024-channel wired AFE redesign; taped out | |||
|- | |||
| [[RC2.0]] || TSMC 28nm HPC+ || wireless variant (UWB); currently active | |||
|- | |||
| [[PMU1]] || 180nm || power-management test chip — does '''not''' inherit 28nm defaults | |||
|- | |||
| RC3.0 / RC3.1 || 28nm || future, scaled toward 10k+ channels | |||
|} | |||
== Start here == | |||
* [[Blocks]] — the signal-chain building blocks (durable theory + per-chip instances) | |||
* [[Decisions]] (ADRs) — the load-bearing record of what was chosen and why | |||
* [[Methods]] — cross-cutting, chip-independent procedures | |||
* [[Timeline]] — the immutable weekly slides & meeting minutes archive | |||
Latest revision as of 09:13, 4 September 2026
Retina Chip Documentation System — the live, present-state knowledge base for the high-channel-count implantable neural-interface ASIC.
The diagram below is the retina chip signal chain. Click any block to open its wiki page.
About this wiki
This wiki follows two hard rules:
- Two genres, never merged — the Timeline is an immutable, append-only chronological record of what was believed on a date. Wiki pages are statements of what is true now. They are never merged.
- Durable vs instance — every block splits into a durable page (what the block is, design equations, budgeting procedure — true independent of any chip) and instance pages (component values, sizing, post-PEX numbers, errata for a specific silicon). A chip page is a thin manifest linking to its instances.
The chips in scope
| Chip | Node | Role |
|---|---|---|
| RC1.9 | TSMC 28nm HPC+ | 1024-channel wired AFE redesign; taped out |
| RC2.0 | TSMC 28nm HPC+ | wireless variant (UWB); currently active |
| PMU1 | 180nm | power-management test chip — does not inherit 28nm defaults |
| RC3.0 / RC3.1 | 28nm | future, scaled toward 10k+ channels |